A Bachelors/Masters/Phd Degree in engineering from Teir I (IIT/NIT/IISC only), with exceptional academic credentials ... GDS2 tapeout. As an integral member of the customer design engineering team, the ASIC Customer Engineer has... full job description

Physical Design , Design Verification, STA, Synthesis, DFT Engineer.Experience - 3 yrs - 10 yrs Job Location - BangaloreWalk-in Venue details - Synapse Techno Design Innovations Pvt Ltd Ferns Icon Bldg, Mezzanine & 1st Floor Doddanekundi... full job description

DFT ENGINEER Job ID 1490761 Location India, Bangalore Description DFT ENGINEER #1490761 As a DFT engineer at NVIDIA, ... Design and verification back ground with experience in STA. - Must possess a strong knowledge of DFT including... full job description

and Wireless Group Job Description Principal ASIC Design Engineer: Architect and Design 4G-LTE mobile wireless ... City/Town Bangalore Shift 1st Shift - Day Percent of Travel Required 5% - 10% Function Engineering Discipline IC... full job description

Job Description Job Description: Senior Staff ASIC Design Engineer: Architect and Design 4G mobile wireless ASIC's. ... City/Town Bangalore Shift 1st Shift - Day Percent of Travel Required 5% - 10% Function Engineering Discipline IC... full job description

Good understanding and knowledge on all aspects of Backend ASIC design flow (Synthesis/DFT/Floor Planning/STA/Layout/Place & Route/Cross talk & Power Analysis/Physical Verification). Knowledge on LVS, DRC is desired - Excellent... full job description

Top/Block level timing closure with sign off STA. Scan chain reordering. Top/Block level ECO implementation involving netlist level logical changes. Scripting experience in Perl/TCL. Library performance analysis and fine tuning for... full job description

some details about AMD India: www.AMD.com The AMD India Engineering Centre is a wholly owned subsidiary of AMD, ... brand new facility at Whitefield, Bangalore. The AMD India Engineering Centre (AMD IEC) will develop leading edge... full job description

Experience : 8-11 years Education : Bachelors / Masters in Engineering or equivalent * Should lead a SOC DFT team * Tech ... * Should be able to drive STA constraints development and support * Memory bist (MBIST/memBIST/PBIST) understanding * Cr... full job description

Top/Block level timing closure with sign off STA. Scan chain reordering. Top/Block level ECO implementation involving netlist level logical changes. Scripting experience in Perl/TCL. Library performance analysis and fine tuning for... full job description

Annual Business Plan. 3) Coordination with procurement, engineering, vendors for supply of material, execution ... & Monitoring usi, Project progress. Budgeting, preparing Billing sch, Coordination with procurement, engineering,... full job description

Product VerificationASIC Design/Verification/PD/Synthesis/STA/Custom Layout. Job Description Design & Development of ... & Experience Min Bachelor degree in Electronics or Computer Engineering Min 2 years of test engineering experience... full job description

4052BR Job Posting Title BPEDA - Timing Engineer Job Description Responsible for definition and development of signoff ... Field(s) of Study Computer Science Electronics & Comm Engineering Minimum Years of Experience 3 Regular /... full job description

Date 05/10/2012 Division Qualcomm CDMA Technology Job Area Engineering - Hardware Location India - Bangalore Job ... Education Requirements BS or MS or Ph.D. in Computer Engineering, Electrical Engineering or Computer... full job description

STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug. Programming in Perl, tcl, ... Design Engineer Functional Area Engineering Design, R&D Education UG - B.Tech/B.E... full job description

RTL and verification back ground with exposure to STA utilizing industry standard tools. Must possess a strong ... Understanding of ATE and test engineering. Post-Silicon debug. Programming in Perl, tcl, awk and c/c++. Experience in... full job description

Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools. Must possess a ... STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug. Programming in Perl, tcl,... full job description

We are looking for Physical Design Engineering with 3 - 7 years experience for Bangalore location & ... timing) rapidly via scripting. Good exposure to: Top level STA & constraints, Physical verification, formal... full job description

We are looking for Physical Design Engineering with 3 - 7 years experience for Bangalore location & Onsite ... Good exposure to: Top level STA & constraints, Physical verification, formal verification Tool Expertise: Talus/ICC Year... full job description

STA / TIMING Engineer (2-8 Yrs exp) # Worked on full chip synthesis using Synopsys DC / Cadence RC compiler # Experience ... speed I/O timing Desired Candidate ProfileSTA / TIMING Engineer (2-8 Yrs) with B.Tech/ Masters in Electronics. #... full job description

: Applications engineer to support WLAN issues in customer mobile phone designs using Qualcomm solution Skills ... environment is highly desired o Prior experience with WLAN STA/softAP/P2P technologies o Good experience in C/C++... full job description

environments. * Knowledge of Synthesis, STA and DFT * Experience with Post Silicon validation * Strong communication, analytical and documentation skills * B.Tech 15+ years or above Job Requirements * Architect and Design 4G (LTE) /... full job description

of Backend ASIC design flow (Synthesis/DFT/Floor Planning/STA/Layout/Place & Route/Cross talk & Power Analysis/Physical Verification). * Knowledge on LVS, DRC is desired - Excellent written/verbal communication skills with ability to work... full job description

advance timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow * Enhance ... in developing and supporting a fully automated STA scripts/flows * Good understanding of deep submicron parasitic... full job description

Position: Sr. Performance Test Engineer Essential Skills: • Have minimum 6 and maximum of 9 years of experience and ... Performance Testing, Load Runner,Test Execution, J Meter,Open STA,WAS,HP Mercury Tool,QC,Quality... full job description

design" Function IT Role Hardware Design Engineer Industry • Telecom • Semiconductor Posted On 14th ... Requirements: BS or MS or Ph.D. in Computer Engineering, Electrical Engineering or Computer... full job description

y challenging Timing, Area & power budgets. Hands on experience on Clock Planning & Implementation, Implementing ECO’s (functional & timing) rapidly via scripting. Good exposure to Top level STA & constraints, Physical verification,... full job description

for the Job Requirement given below Hands on experience in STA & Synthesis Working knowledge of Timing Analysis, physical verification, signal integrity issues Hands on experience from post RTL to GDSII for atleast minimum 5 Chips Strong... full job description

signal integrity issues (Including Primetime STA, Calibre DRC/LV, EM/IR analysis using Apache Redhawk etc) Working knowledge of basic circuit design (Including exposure to Hspice etc) Exposure to SRAM memory design is desirable Ability to... full job description

in drawing analysis, FMEA, Control Plans, knowledge engineering, manufacturing technologies, APQP, PPAP, QA Systems like TS, ISO, 5*, etc.....and willing to relocate to Chennai need to apply Experience Required: 3 to 6 Education... full job description

A Life Time Opportunity as a Application Engineer in Lead EDA Company!!! > Role: > Your role will be to meet customers/p ... TCL > - Strong understanding of Design logic and ASIC flow, STA etc. > - Strong knowledge on ibis char methodology,... full job description

in drawing analysis, FMEA, Control Plans, knowledge engineering, manufacturing technologies, APQP, PPAP, QA Systems like TS, ISO, 5*, etc.....and willing to relocate to Chennai need to apply Experience Required: 8 to 13 Education... full job description

STA / TIMING Engineer (2-8 Yrs exp) # Worked on full chip synthesis using Synopsys DC / Cadence RC compiler # Experience ... speed I/O timing Desired Candidate ProfileSTA / TIMING Engineer (2-8 Yrs) with B.Tech/ Masters in Electronics. #... full job description

Digital logic Circuit theory SoC architecture ARM based SoC STA Design Validation & Verification Desired Candidate ProfilePlease refer to the Job description above Experience Required: 2 to 6 Education Required: (UG - B.Tech/B.E.) OR... full job description

STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug. Programming in Perl, tcl, ... Design Engineer Functional Area Engineering Design, R&D Education UG - B.Tech/B.E... full job description

are looking for an experienced VLSI ASIC implementation engineer. Candidate will work closely with Implementation ... code-review/linting, constraint building and integration, STA, formal checking, ECO changes are essential. Well... full job description

Type Semiconductors, Electronics Role Testing Engineer Functional Area Embedded/EDA /VLSI/ASIC/Chip ... Bengaluru/Bangalore Keywords DFT, ATPG, Perl, STA Synthesis, Test Pattern Contact Maxim India Integrated... full job description

In this position, the individual will be responsible for Synthesis/STA using Design Compiler and Prime Time ... Mentoring and supporting junior engineers Desired Profile Bachelor or Master Degree in Electrical/Electronics Engineer... full job description

are looking for an experienced VLSI ASIC implementation engineer. Candidate will work closely with Implementation ... code-review/linting, constraint building and integration, STA, formal checking, ECO changes are essential. Well... full job description

design of complex Chip/IPs. • Participate in STA and Timing Closure activities. • Work with chip integration team closely in Timing closure. • Complete the Block level/SoC Design including the Physical Design Verification. •... full job description

design of complex Chip/IPs. • Participate in STA and Timing Closure activities • Work with chip integration team closely in Timing closure • Complete the Block level/SoC Design including the Physical Design Verification • Participate... full job description

SENIOR DFT ENGINEER #1429522 As a DFT engineer at NVIDIA, you'll be responsible for cutting edge DFT involving ... Design and verification back ground with experience in STA. - Must possess a strong knowledge of DFT including... full job description

design linting, Emulation, Floorplanning, Place&Route, STA, Physical Verification. * Strong knowledge in software development and/or scripting using Perl, TCL, C/C++, Makefiles, or UNIX shell languages. * Experience with design management... full job description

customer design engineering team, the ASIC Customer Engineer has responsibility for a wide range of tasks, including ... and for interfacing to many different people and engineering teams within LSI. Position requires weekly interface with... full job description

implementation • Responsibilities include synthesis, STA and LEC of low power designs • Generating and validating timing (SDC) and power constraints (UPF, CPF) • Generating RTL glue logic required to integrate design • Interacting with... full job description

Hi-tech Semiconductor space. As a Staff Design Engineer (Engineering Manager) in the Architecture, Timing and ... 5.Spice simulations 6.Understanding of statistical STA 7.Characterization of silicon for timing 8.FPGA design... full job description

Physical design of complex Chip/IPs. • Participate in STA and Timing Closure activities • Work with chip integration ... Experience should be focused on design implementation. • Masters in Engineering/ Bachelors in Engineering from a rep... full job description

Physical design of complex Chip/IPs. • Participate in STA and Timing Closure activities • Work with chip integration team closely in Timing closure • Complete the Block level/SoC Design including the Physical Design Verification •... full job description

flow and develop synthesis constraints Experience in STA and timing closure activities and coming up with STA ... Should be able to setup and own/drive the STA and timing closure activities for the design... full job description

Top/Block level timing closure with sign off STA. Scan chain reordering. Top/Block level ECO implementation involving netlist level logical changes. Scripting experience in Perl/TCL. Library performance analysis and fine tuning for... full job description

Dear Candidates , we have openings for STA / Synthesis Engineer with an leading MNC Bangalore STA / Synthesis EngineerOp ... to Face Interview on Saturday 12th May 2012 Designation : STA / Synthesis Engineer Location : Bangalore Qualification... full job description

usage challenges. - You will be interfacing with our Design Engineering team to report on any issues related to the IP’ ... and flows in the areas of Synthesis, Simulation, STA, Verification, Testability, Place and Route, Design Reuse... full job description

Engineer - 2- 10 Years 3) DFT Engineer - 2 - 8 Years 4) STA / Synthesis Engineer - 3 - 10 Years Interested professionals kindly forward your updated resume to prejith(at)roljobs.com. For further details reach us on 080 - 42821621 Contact... full job description

1.Worked on 45 nm 2.Experience on Synthesis 3.Experience on STA 4.Should have worked on Synthesis using RTL complier 5.Should have worked on STA using Gold Time 6.Should be good at Flow and methodology If interested Send CV to... full job description

Roland & Associates Jobs for STA / Synthesis Engineer With an MNC Bangalore Roland & Associates is an recruiting company ... Candidate Requirement Designation : STA / Synthesis Engineer Location : Bangalore Qualification... full job description

Requisition Number: 12-9021 Job Title: PD Engineer Senior Country: India State/Province/County: Karnataka City: Bangalor ... Masters in Engineering/ Bachelors in Engineering from a reputed institute with good academic record Experience:... full job description

If Interested, Please Send a copy of your CV @ ashish.singh@nsoftindia.com # STA / TIMING Engineer (2-8 Yrs) with B.Tech/ Masters in Electronics. # Worked on full chip synthesis using Synopsys DC / Cadence RC compiler # Experience with... full job description

Magma TALUS or Synopsys ICC. 3. Good Knowledge on PrimTime STA # Physical implementation of high performance processor, DSP & Graphics cores. # Activities include floorplanning, PnR, Clock Tree Synthesis, Timing closure, Power analysis,... full job description

Job Location : Ahmedabad, Gujrat Education Qualification :Engineering degree / Diploma/CDP.(Mechanical) Number of Years ... automotive back ground, MFE, Supply chain, Packaging Engineering experience is preferred Position... full job description

Senior Quality Assurance Engineer Developer Openings with a Product Development Company in Bangalore Experience: 3-6 ... wireless network (controller / Access point / STA) including signaling servers, network... full job description

C and PERL is preferred. * Knowledge of FPGA. * Exposure in STA. * Must have completed at least one front-end design cycle. * Should definitely have Synthesis (Synopsys DC) and Simulation(Verilog-XL/NC or VCS) tool knowledge. * Sound... full job description

in communications technologies. Challenge Yourself! Engineer, Principal - IC Design * In this role you will ... Principal - IC Design Role: • Hardware Design Engineer • Other... full job description

Degree in Electrical/Electronics/Computer science engineering · Experience level in the range of 3 to 5 years · ... level/small chip Place & Route, Timing closure(STA) · Strong knowledge of clock tree synthesis, SI analysis,... full job description

Degree in Electrical/Electronics/Computer science engineering with at least 8 to 10 years of experience in ... software development * Experience in leading full-chip STA closure, defining mode requirements and corners for timing... full job description

in communications technologies. Challenge Yourself! Engineer, Sr Principal - IC Design Description * 10+ years ... Sr Principal - IC Design Role: Hardware Design Engineer Location: Bangalore Industry: Telecom Posted... full job description

teams participation in all the key meetings viz., weekly engineering change control , TVM , VRT / Quality / CAL , ... customer audio & C&L meetings , obsolescence , purchasing / STA , finance and all MP&L cross functional meetings . 9)... full job description

STA Physical Design Engineer Job Location-Noida Your main duties will be: *Full chip timing constraints development, ... timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow *Enhance existing entire... full job description

timing (SDF) Closing working with Test Engineer and Product Engineer team to understand testability requirement for ... Master/Bachelor's Degree in Electrical/Electronic Engineering 3-8 year(s) of working experience in DFT Must... full job description

nodes like 32/45/65/90 · Synthesis and STA is nice to have · Hands on in Synopsys/Mentor/Cadence DFT Tools · Perl and Unix · Scripting and automation Soft Skills · High Integrity · Problem solving skills and learning attitude · Good... full job description

Excellent knowledge of IEEE 802.11a/b/g/h/i/e/n standards Good experience in developing compliance test suite for IEEE 802.11 standards Should have experience in protocol testing of 802.11 Should be ble to configure STAs and APs from... full job description

the globe Required skill(s) : Purchasing, STA, MP& L Experience Required: 8 to 10 Education Required: (UG - Any Graduate - Any Specialization, B.Tech/B.E. - Any Specialization) OR (PG - Post Graduation Not Required) Address:... full job description

We need Physical Design Engineers who are good at Synthesis/EC, PnR/CTS (Cadence preferred), Timing Constraints, STA, Backend checks and Electrical analysis. Experience : 3- 8 years Work Location: Bangalore or Noida Title : Senior... full job description

teams participation in all the key meetings viz., weekly engineering change control , TVM , VRT / Quality / CAL , ... audio & C& L meetings , obsolescence , purchasing / STA , finance and all MP& L cross functional meetings . 9)... full job description

verification, signal integrity issues (Including Primetime STA, Calibre DRC/LV, EM/IR analysis using Apache Redhawk etc) Working knowledge of basic circuit design (Including exposure to Hspice etc) Exposure to SRAM memory design is... full job description

nodes along with exp in Floor planning, Placement, CTS,STA,PnR, routing, Signal integrity,DRC,EDA Tools like Talus, ICC, First Encounter,Pinnacle, Olympus,... full job description

Tech in Electrical Engineering, Computer Engineering, VLSI * Prior industry experience in synthesis and STA. * Strong Di ... The position as a SoC/IP synthesis and STA engineer requires rigorous interactions with the specifications team, systems... full job description

Synthesis & STA Engineer Primary Responsibilities: • Synthesis & timing closure of IP and/or SoC meeting all PPAS goals ... of below: • Work with other synthesis and STA teams to share best practices. • Interact with the Software and... full job description

understanding of static timing analysis (STA) and sign-off flows * Strong hands-on experience with floorplanning, place & route, power and clock distribution, timing analysis and closure with signal integrity, EM/IR and physical design... full job description

standard tools in the domains of Logic/ Physical Synthesis, STA, Timing Optimization, Floorplanning, Place and Route. * Understanding of nanometer design challenges. * Proficiency in writing and understanding Verilog, VHDL and Mixed... full job description

ENGR I (Digital Design) Job ID 11116 Location Bangalore, India Category Engineering Relocation Approved? Yes - Regional ... Position Description As a Digital/Mixed-Signal Design Engineer, responsibilities will include: .Advanced digital... full job description

/ configure wireless network (controller / Access point / STA) -Responsible for writing and executing test plans/cases for installation / configuration, functional/ integration / regression, performance, load, stress etc for 802.11... full job description

Requirement : Category :Semiconductor Jobs Designation : Synthesis/STA Location :Bangalore Qualification:BE or ME / MTec ... 45 etc.) • Experience on Synthesis • Experience on STA • Should have worked on Synthesis using RTL complier or Design... full job description

nodes (90, 65, 45 etc.) Experience on Synthesis & STA Should have worked on Synthesis using RTL complier or Design Compiler Should have worked on STA using Gold Time or Primetime Should be good at Flow and... full job description

Educational Qualification: Bachelors or Masters Degree in Engineering - 5+ years of experience in DFT - Strong ... complex digital logic blocks - Experience in verification, STA and defining timing constraints for DFT modes -... full job description

in communications technologies. Challenge Yourself! Engineer, Principal Physical Design * Job involves owning ... Principal Physical Design Role: Hardware Design Engineer Location: Bangalore Industry: Telecom Posted... full job description

in communications technologies. Challenge Yourself! Engineer, Staff I - IC Design * In this role, the candidate ... Staff I - IC Design Role: • Hardware Design Engineer • Other... full job description

rapidly via scripting. o Good exposure to Top level STA & constraints, Physical verification, formal verification o Should have worked on Implementing Cores or Hard macros with very tight timing constraints before. Job... full job description

of Ethernet MAC, SDIO. 7. Experience with synthesis, STA and sdc constraints. 8. Highly motivated and independent contributor 9. Need to be well organized, methodical, and detail oriented Job Requirements : 1. VLSI (M.E./ M. full job description

QA Engineer Openings with the Product Development Company in Bangalore Experience: 5-8 years Location: ... wireless network (controller / Access point / STA) including signaling servers, network... full job description

PV) Well versed with the top/block level timing closure (STA), timing closure methodologies. Well versed with ... resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow... full job description

2) SOC/IP DFT Engineer (1 to 8 Yrs) Good Basic understanding of all concepts of DFT including scan, ATPG, Memory Testing ... system modeling and functional modeling a plus 4) ASIC STA Engineer (2 to 8 Yrs) Should have good timing concepts... full job description

including VHDL design, simulation, synthesis, Place/Route, STA & Implementation. * Familiarity with FPGA technologies (Actel / Xilinx / Altera). Experience with the following software tools: * VHDL simulator – (Modelsim, Active... full job description

(SDF) * Closing working with Test Engineer and Product Engineer team to understand testability requirement for ... Master/Bachelor's Degree in Electrical/Electronic Engineering * 3-8 year(s) of working experience in DFT *... full job description

Position: Physical Design Engineer Location: Bangalore Experience: 2 – 10 yrs Qualification: B.E / B.Tech / M.E / M. ... Timing closure, Power Planning,IO planning * Synthesis,STA,MAGMA,ICC, * Primetime,PTSI,Design... full job description

internal teams - IP, Packaging, marketing , product engineering and coordinate the activities effectively * Work with tool vendors to eliminate issues in execution * Plan work load to allow shortest TAT while ensuring all quality... full job description

RTL coding * ASIC/FPGA Tool flow (synthesis / P&R / STA / Debug) * Diagnostic tools Scope, Logic Analyzer * Good understanding of HW circuits and board schematics * Embedded SW, C/Assembly level programming, Scripting * In depth... full job description

Requisition # G1899499 Job Title Physical Design Engineer (3-7 years of experience) Post Date 05/08/2012 Division Qualco ... Responsibilities Education Requirements Masters/Bachelors Degree in Electrical/Electronics science engineering... full job description

. B.Tech/M.Tech in Electronics Engineering/Electrical Engineering, VLSI . Prior Industry experience in STA and ... The position as a SoC/IP STA engineer requires rigorous interactions with the specifications team, systems engineering t... full job description

B.Tech/M.Tech in Electronics/Electrical Engineering, VLSI ... rigorous interactions with the specifications team, systems engineering team, RTL, DFT, DV and STA engineers. Projects... full job description

B.Tech/M.Tech in Electronics Engineering/Electrical Engineering, VLSI ... team, systems engineering team, verification, DFT, STA and the physical design engineers. Projects and... full job description